1. Field of the Invention
The present invention relates to a Liquid-Crystal Display (LCD) and more particularly, to an active-matrix type LCD having a plurality of Thin-Film Transistors (TFTS) arranged in a matrix array.
2. Description of the Prior Art
In recent years, active-matrix type color LCDs have been widely used as electronic display devices for personal computers, portable televisions, or the like, because they are low in power dissipation, thin, light-weight, and good in image quality. A typical example of the configuration of these LCDs is shown in FIG. 1.
As shown in FIG. 1, this color LCD is comprised of pixel electrodes 101 arranged in a matrix array with m rows and 3n columns, where m and n are natural numbers. Therefore, the total number of the pixel electrodes 101 is (m.times.3n).
A group of the (m.times.n) pixel electrodes 101 are used for displaying the red (R) color, forming R subpixels. Another group of the (m.times.n) pixel electrodes 101 are used for displaying the green (G) color, forming G subpixels. The remaining (m.times.n) pixel electrodes 101 are used for displaying the blue (B) color, forming B subpixels. Thus, the total number of pixels or dots of this color LCD is (m.times.n).
First to m-th scanning lines or electrodes 102(1) to 102(m) are arranged along the respective rows of the matrix array. First to 3n-th data lines or electrodes 103(1) to 103(3n) are arranged along the respective columns of the matrix array. (M.times.3n) TFTs 106 are arranged at the respective intersections of the scanning lines 102(1) to 102(m) and the data lines 103(1) to 103(3n), driving the respective (m.times.3n) pixel electrodes 101.
The scanning lines 102(1) to 102(m) are driven or controlled by a scanner driver circuit 104. The data lines 103(1) to 103(3n) are driven or controlled by a data driver circuit 105.
Each of the (m.times.3n) TFTs 106 has a gate electrically connected to a corresponding one of the scanning lines 102(1) to 102(m), a drain electrically connected to a corresponding one of the data lines 103(1) to 102(3n), and a source electrically connected to a corresponding one of the (m.times.3n) pixel electrodes 101.
For example, if the conventional LCD with the configuration shown in FIG. 1 has a resolution of (640.times.480) pixels or dots according to the Video Graphics Array (VGA) standard, the number of the scanning lines is 480, the number of the data lines is 1920 (=640.times.3), and the number of the pixel electrodes 101 is 1920 (=640.times.3).
Typically, the data driver circuit 105 needs to produce output voltages with more than two levels (e.g., 6 levels or more) to the data lines 103(1) to 103(3n) in order to display a required color image. On the other hand, it is sufficient for the scanner driver circuit 104 to produce output voltages with only two levels (i.e., high and low levels) to the scanning lines 102(1) to 102(m) in order to scan these lines 102(1) to 102(m). Therefore, the data driver circuit 105 is more expensive compared with the scanner driver circuit 104, resulting in a problem that the color LCD is high in fabrication cost.
To solve this problem, an improved configuration of the active-matrlx type color LCDs is shown in FIG. 2. This configuration is disclosed in, for example, the Japanese Non-Examined Patent Publication Nos. 3-38689 published in February 1991, 5-265045 published in October 1993, and 6-148680 published in May 1994.
As shown in FIG. 2, a plurality of pixel electrodes 201 are arranged in a matrix array with 2m rows and (3/2)n columns. The total number of these pixel electrodes 201 is 3(m.times.n).
A group of the [(2/3)m.times.(1/2)n] pixel electrodes 201 are used for displaying the red (R) color, forming R subpixels. Another group of the [(2/3)m.times.(1/2)n] pixel electrodes 201 are used for displaying the green (G) color, forming G subpixels. The remaining [(2/3)m.times.(1/2)n] pixel electrodes 201 are used for displaying the blue (B) color, forming B subpixels. Thus, the total number of pixels or dots of this color LCD is (m.times.n) (=3[(2/3)m.times.(1/2)n]).
First to 2m-th scanning lines 202(1) to 202(2m) are arranged along the respective rows of the matrix array. First to (3/2)n-th data lines 203(1) to 203(3n/2) are arranged along the respective columns of the matrix array. 3(m.times.n) TFTs 206 are arranged at the respective intersections of the scanning lines 202(1) to 202(2m) and the data lines 203(1) to 203(3n/2).
The scanning lines 202(1) to 202(2m) are driven by a scanner driver circuit 204. The data lines 203(1) to 203(3n/2) are driven by a data driver circuit 205.
The electrical connection of the TFTs 206 to the scanning lines 202(1) to 202(2m), the data lines 203(1) to 203(3n/2), and the pixel electrodes 201 is shown in detail in FIG. 3.
In FIG. 3, a part 200 of the matrix array is Illustrated, which includes the intersections of the (j-1)-th and j-th data lines 203(j-1) and 203(j) with the i-th, (i+1)-th, (i+2)-th, and (i+3)-th scanning lines 202(i), 202(i+1), 202(i+2), and 202(i+3), and their neighborhood. Here, i and j are natural numbers satisfying the relationships of 1.ltoreq.i.ltoreq.2m and 1.ltoreq.j.ltoreq.3n/2.
The TFT 206(i, j), which is located at the intersection of the i-th scanning line 202(i) and the j-th data line 203(j), has a gate electrically connected to the i-th scanning line 202(i), a drain electrically connected to the j-th data line 203(j), and a source electrically connected to the corresponding pixel electrode 201(i, j). Similarly, the TFT 206(i+1, j), which is located at the intersection of the (i+1)-th scanning line 202(i+1) and the j-th data line 203(j), has a gate electrically connected to the (i+1)-th scanning line 202(i+1), a drain electrically connected to the j-th data line 203(j), and a source electrically connected to the corresponding pixel electrode 201(i+1, j). Thus, the j-th data line 203(j) Is commonly used by the two TFTs 206(i, j) and 206(i+1, j). The i-th and (i+1)-th scanning lines 202(i) and 202(i+1) are respectively used by these two TFTs 206(i, j) and 206(i+1, j).
The TFT 206(i, j-1), which is located at the intersection of the i-th scanning line 202(i) and the (j-1)-th data line 203(j-1). has a gate electrically connected to the i-th scanning line 202(i), a drain electrically connected to the (j-1)-th data line 203(j-1), and a source electrically connected to the corresponding pixel electrode 201(i, j-1). Similarly, the TFT 206(i+1, j-1), which is located at the intersection of the (i+1)-th scanning line 202(i+1) and the (j-1)-tb data line 203(j-1), has a gate electrically connected to the (i+1)-th scanning line 202(i+1), a drain electrically connected to the (j-1)-th data line 203(j-1), and a source electrically connected to the corresponding pixel electrode 201(i+1, j-1). Thus, the (j-1)-th data line 203(j-1) is commonly used by the two TFTs 206(i, j-1) and 206(i+1, j-1). The i-th and (i+1)-th scanning lines 202(i) and 202(i+1) are respectively used by these two TFTs 206(i, j-1) and 206(i+1, j-1),
The TFT 206(i+2, j-1), which is located at the intersection of the (i+2)-th scanning line 202(i+2) and the (j-1)-th data line 203(j-1), has a gate electrically connected to the (i+2)-th scanning line 202(i+2), a drain electrically connected to the (j-1)-th data line 203(j-1), and a source electrically connected to the corresponding pixel electrode 201(i+2, j-1). Similarly, the TFT 206(i+3, j-1), which is located at the intersection of the (i+3)-th scanning line 202(i+3) and the (j-1)-th data line 203(j-1), has a gate electrically connected to the (i+3)th scanning line 202(i+3), a drain electrically connected to the (j-1)-th data line 203(j-1), and a source electrically connected to the corresponding pixel electrode 201(i+3, j-1). Thus, the (j-1)-th data line 203(j-1) is commonly used by the two TFTs 206(i+2, j-1) and 206(i+3, j-1). The (i+2)-th and (i+3)-th scanning lines 202(i+2) and 202(i+3) are respectively used by these two TFTs 206(i+2, j-1) and 206(i+3, j-1).
The TFT 206(i+2, j), which is located at the intersection of the (i+2)-th scanning line 202(i+2) and the j-th data line 203(j), has a gate electrically connected to the (i+2)-th scanning line 202(i+2), a drain electrically connected to the j-th data line 203(j), and a source electrically connected to the corresponding pixel electrode 201(i+2, j). Similarly. the TFT 206(i+3, j). which is lodated at the intersection of the (i+3)-th scanning line 202(i+3) and the j-th data line 203(j), has a gate electrically connected to the (i+3)-th scanning line 202(i+3), a drain electrically connected to the j-th data line 203(j), and a source electrically connected to the corresponding pixel electrode 201(i+3, j). Thus, the j-th data line 203(j) is commonly used by the two TFTs 206(i+2, j) and 206(i+3, j). The (i+2)-th and (i+3)-th scanning lines 202(i+2) and 202(i+3) are respectively used by these two TFTs 206(i+2, j) and 206(i+3, j).
As described above, with the improved configuration shown in FIG. 2, two ones of the scanning lines 202(1) to 202(2m) are provided for each row of the matrix array of the pixels and each of the data lines 203(1) to 203(3n/2) is commonly used by two adjoining columns thereof. Accordingly, the number of the necessary scanning lines is 2m and the number of the necessary data lines is (3n/2) for (m.times.n) color pixels.
For example, if the conventional LCD has a resolution of (640.times.480) pixels according to the VGA standard. the number of the necessary scanning lines is 960 (=480.times.2), the number of the necessary data lines is 960 (=640.times.3/2), and the number of the pixel electrodes is 960 (=640.times.3/2).
Therefore, with the improved configuration shown in FIGS. 2 and 3, the number of the necessary data lines is decreased to a half of that of the conventional configuration shown in FIG. 1. As a result, the fabrication cost of the data driver circuit is able to be reduced.
Next, a driving method of the conventional LCD with the improved configuration shown in FIGS. 2 and 3 will be explained below with reference to FIGS. 3 and 4A to 4E.
In this driving method, the scanning lines 202(1) to 202(2m) are successively activated from the first scanning line 202(1) to the last or 2m-th scanning line 202(2m). The data lines 203(1) to 203(3n/2) are successively activated from the first data line 203(1) to the last or (3n/2)-th data line 203(3n/2) synchronized with the activation behavior of the scanning lines 202(1) to 202(2m), thereby displaying a required color image. These scanning and data-writing processes are the same as those that have ever been known well.
However, unlike the well-known popular scanning processes, a scanning period for each row of the matrix array is divided into two subperiods, i.e., earlier and later subperiods. For example, in FIG. 3, the pixel electrodes 201(i, j) and 201(i, j-1) electrically connected to the scanning line 202(1) are driven or written during the earlier subperiod. The pixel electrodes 201(i+1, j) and 201(i+1, j-1) electrically connected to the scanning line 202(i+1) are driven during the later subperiod. Similarly, the pixel electrodes 201(i+2, j) and 201(i+2, j-1) electrically connected to the scanning line 202(i+2) are driven during the earlier subperiod. The pixel electrodes 201(i+3, j) and 201(i+3, j-1) electrically connected to the scanning line 202(i+3) are driven during the later subperiod.
Thus, the pixel electrodes 201(i, j), 201(i+1, j), 201(i+2, j), and 201(i+3, j), which are electrically connected in common to the data line 203(j), are successively activated in this order. This means that the activation or driving order is along an arrow y shown in FIG. 3. The pixel electrodes 201(i, j-1), 201(i+1, j-1), 201(i+2, j-1), and 201(i+3, j-1), which are electrically connected in common to the data line 203(j-1), are successively activated in this order along an arrow x shown in FIG. 3.
Because the arrow y is inverted with respect to the arrow x, this driving or activation method is termed the "U-inverted U" type.
The conventional LCD with the improved configuration shown in FIGS. 2 and 3, which is activated by the method of the "U-inverted U" type, has the following problem.
For example, as shown in FIG. 4B, when the i-th scanning line 202(1) is applied with a scanning signal G(i) of a voltage level V.sub.g (in other words, the i-th scanning line 202(i) is activated) during an earlier subperiod TH1 (which starts at the time T1 and ends at the time T2), a data signal D(j) of a high-level voltage V.sub.m is applied to or written in the pixel electrode 201(i, j) through the data line 203(j). Thus, the voltage of the pixel electrode 201(i, j) is turned from a low-level voltage V.sub.n to the high-level voltage V.sub.m at the time T1, and it is kept unchanged during the earlier uubperiod TH1, as shown in FIG. 4D.
Next, when the (i+1)-th scanning line 202(i+1) is applied with a scanning signal G(i+1) of the same voltage level V.sub.g (in other words, the (i+1)-th scanning line 202(i+1) is activated) during a later subperiod TH2 (which starts at the time T2 and ends at the time T3), as shown in FIG. 4C, the data signal D(j) of the low-level voltage V.sub.n is applied to or written in the pixel electrode 201(i+1, j) through the same data line 203(j). Thus, the voltage of the pixel electrode 201(i+1, j) is turned from the high-level voltage V.sub.m to the low-level voltage V.sub.n at the time T2, and it is kept unchanged during the later subperiod TH2, as shown in FIG. 4E.
During the later subperiod TH2, the voltage of the pixel electrode 201(i, j) is lowered from the high-level voltage V.sub.m by a voltage deviation V.sub.pp, resulting in a problem that the display quality of the LCD is degraded. This problem is due to a parasitic capacitor C1 between the two adjoining pixel electrodes 201(i, j) and 201(i+1, j) which are located at each side of the corresponding data line 203(j).
The voltage deviation V.sub.pp can be expressed as EQU V.sub.pp =(C.sub.1 /C.sub.tot).multidot..DELTA.V.sub.p (1)
where C.sub.1 is the capacitance per unit length of the parasitic capacitor C1, C.sub.tot is the total capacitance per unit length of each pixel electrode, and .DELTA.V.sub.p is the voltage amplitude (i.e., V.sub.m -V.sub.n) of each pixel electrode.
Computer simulation was carried out by the inventor based on the equation (1), presenting the results shown in FIG. 19. The curve A in FIG. 19 indicates the case where a data line exists between two adjoining pixel electrodes, and the curve B indicates the case where no data line exists therebetween.
When the distance L between the opposite ends of the adjoining pixel electrodes is 7 .mu.m, it is seen from the curve A in FIG. 19 that the parasitic capacitance C.sub.1 is 10 pF/m. If the pitch of the pixel electrodes is 300 .mu.m, the parasitic capacitance C.sub.1 is expressed as EQU C.sub.1 =10(pF/m).times.300 .mu.m=0.003 pF.
If the total capacitance of each pixel electrode C.sub.tot is 0.1 pF, and the voltage amplitude .DELTA.V.sub.p of each pixel electrode is 5 V for displaying a medium gradation, the voltage deviation V.sub.pp is expressed as EQU V.sub.pp =[(0.03)/0.1].times.5=0.15 V=150 mV (2)
The expression (2) represents the brightness difference is distinctive for displaying the medium gradation. This means that distinctive brightness difference exists between the pixel electrode 201(i, j) in which the high-level voltage V.sub.m is written during the earlier subperiod TH1 and the pixel electrode 201(i+1, j) in which the high-level voltage V.sub.m is written during the later subperiod TH2.
As a result, when some specified patterns such as a check pattern are displayed on the screen of this LCD, the displayed image includes some defects such as vertical-striped brightness unevenness. This is due to the layout that the pixel electrodes written during the earlier subperiod TH1 and those written during the later subperiod TH2 are vertically aligned along the data lines.
A variation of the above conventional LCD with the improved configuration shown in FIGS. 2 and 3 will be explained below with reference to FIGS. 5 and 6A to 6G. This configuration makes it possible to suppress the above-described defects in the displayed image.
FIG. 5 shows the electrical connection or layout of the pixel electrodes and the TFTs to the scanning and data lines.
In FIG. 5, the positions of the TFTs 206(i, j), 206(i+1, j), 206(i+2, j), and 206(i+3, j) located at the right-hand side are the same as those in FIG. 3. However, the position of the TFT 206(i, j-1) in FIG. 5 is opposite to that of the TFT 206(i+1, j-1), and the position of the TFT 206(i+2, j-1) in FIG. 5 is opposite to that of the TFT 206(i+3, j-1).
A driving method of the conventional LCD with the improved configuration shown in FIG. 5 will be explained below with reference to FIGS. 6A to 6G.
In FIG. 5, the pixel electrodes 201(i, j) and 201(i, j-1) electrically connected to the scanning line 202(i) are driven or written during the earlier subperiod. The pixel electrodes 201(i+1, j) and 201(i+1, j-1) electrically connected to the scanning line 202(i+1) are driven during the later subperiod. Similarly, the pixel electrodes 201(i+2, j) and 201(i+2, j-1) electrically connected to the scanning line 202(i+2) are driven during the earlier subperiod. The pixel electrodes 201(i+3, j) and 201(i+3, j-1) electrically connected to the scanning line 202(i+3) are driven during the later subperiod.
Thus, similar to the method in FIG. 3, the pixel electrodes 201(i, j), 201(i+1, j), 201(i+2, j), and 201(i+3, j), which are electrically connected in common to the data line 203(j), are successively driven or activated in this order. This means that the driving order is along the same arrow y as that shown in FIG. 3.
Unlike the configuration in FIG. 3, the pixel electrodes 201(i, j-1), 201(i+1, j-1), 201(i+2, j-1), and 201(i+3, j-1), which are electrically connected in common to the data line 203(j-1), are successively driven or activated in this order along an arrow x' shown in FIG. 5. The arrow x' corresponds to a mirrored image of the arrow x in FIG. 3.
Because the arrows x' and y are parallel to each other, this driving or activation method is termed the "U--U" type.
For example, as shown in FIG. 6C, when the i-th scanning line 202(i) is applied with a scanning signal G(i) of a voltage level V.sub.g (in other words, the i-th scanning line 202(i) is activated) during an earlier subperiod TH1, a data signal D(j) of a high-level voltage V.sub.m is applied to or written in the pixel electrode 201(i, j) through the data line 203(j). Thus, the voltage of the pixel electrode 201(i, j) is turned from a low-level voltage V.sub.n to the high-level voltage V.sub.m at the time T1, and it is kept unchanged during the earlier subperiod TH1, as shown in FIG. 6E.
Next, when the (i+1)-th scanning line 202(i+1) is applied with a scanning signal G(i+1) of the same voltage level V.sub.g (in other words, the (i+1)-th scanning line 202(i+1) is activated) during a later subperiod TH2. as shown in FIG. 6D, the data signal D(j) of the low-level voltage V.sub.n is written in the pixel electrode 201(i+1, j) through the same data line 203(j). Thus, the voltage of the pixel electrode 201(i+1, j) is turned from the low-level voltage V.sub.n to the high-level voltage V.sub.m at the time T2, and it is kept unchanged during the later subperiod TH2, as shown in FIG. 6G.
Simultaneously with the application of a scanning signal G(i+1) of the same voltage level V.sub.g to the (i+1)-th scanning line 202(i+1) during the later subperiod TH2, as shown in FIG. 6D, the data signal D(j-1) of the low-level voltage V.sub.n is applied to or written in the pixel electrode 201(i+1, j-1) through the data line 203(j-1). Thus, the voltage of the pixel electrode 201(i+1, j-1) is turned from the high-level voltage V.sub.m to the low-level voltage V.sub.n at the time T2, and it is kept unchanged during the later subperiod TH2, as shown in FIG. 6F.
As described above, during the later subperiod TH2, the voltage of the pixel electrode 201(i, j) is lowered from the high-level voltage V.sub.m by a voltage deviation V.sub.pp, thereby causing a problem that the display quality of the LCD is degraded. This problem is due to a parasitic capacitance C1 between the two adjoining pixel electrodes 201(i, j) and 201(i+1, j) which are located at each side of the data line 203(j), and another parasitic capacitance C2 between the two adjoining pixel electrodes 201(i, j) and 201(i+1, j-1) which are located between the data lines 203(j-1) and 203(j).
The voltage deviation V.sub.pp can be expressed as EQU V.sub.pp =[(C.sub.1 -C.sub.2)/C.sub.tot ].multidot..DELTA.V.sub.p(3)
where C.sub.1 and C.sub.2 are the capacitances per unit length of the parasitic capacitors C1 and C2, C.sub.tot is the total capacitance per unit length of each pixel electrode, and .DELTA.V.sub.p is the voltage amplitude (i.e., V.sub.m -V.sub.n) of each pixel electrode. The sign difference between the capacitance C.sub.1 and C.sub.2 is due to the fact that the data signals D(j) and D(j-1) are in opposite levels.
The above expression (3) means that the capacitances C.sub.1 and C.sub.2 serve to cancel their effects with each other. However, these two capacitances C.sub.1 and C.sub.2 are not completely canceled with each other, because they are not equal.
Specifically, the data line 203(j) is located between the pixel electrodes 201(i, j) and 201(i+1, j). Therefore, when the distance L between the opposite ends of the adjoining pixel electrodes 201(i, j) and 201(i+1, j) is 7 .mu.m, it is seen from the curve A in FIG. 19 that the parasitic capacitance C.sub.1 is 10 pF/m. On the other hand, no data line is located between the pixel electrodes 201(i, j) and 201(i+1, j-1) and therefore, the parasitic capacitance C.sub.2 is approximately 30 pF/m, which is greater than the parasitic capacitance C.sub.1. Thus, the parasitic capacitances C.sub.1 and C.sub.2 are not completely canceled with each other.
If the total capacitance of each pixel electrode C.sub.tot is 0.1 pF, and the voltage amplitude .DELTA.V.sub.p of each pixel electrode is 5 V for displaying a medium gradation, the voltage deviation V.sub.pp is expressed as EQU V.sub.pp ={[(10-30).times.300]/0.1]}.times.5=-0.3 V=-300 m V(4)
The expression (4) represents the brightness difference is distinctive for displaying the medium gradation. This means that distinctive brightness difference exists between and the adjoining pixel electrodes 201(1, j) and 201(i+1, j),
As a result, although the displayed image does not include the previously-described defects such as vertical-striped brightness unevenness in the configuration of FIG. 3, the displayed image includes some other defects such as regular brightness unevenness when no pattern is displayed (i.e., a solid image is displayed) on the screen of this LCD. This is due to the layout that the pixel electrodes written during the earlier subperiod TH1 are laid out between those written during the later subperiod TH2 along the scanning lines.
As understood from the above explanation, the above-described conventional improved configuration shown in FIGS. 3 and 5 has a problem that some brightness unevenness degrades the image quality.
Additionally, to solve this problem, another improved configuration of the active-matrix type color LCDs was developed, which is disclosed in the Japanese Non-Examined Patent Publication No. 63-202792 published in August 1988.
In this conflguration, an electrically conductive film is provided over a data line through a passivation film. The conductive film is applied with a fixed voltage. The parasitic capacitance between the data line and adjoining pixel electrodes is suppressed by shielding the electric field directed from the data line toward the pixel electrodes.
However, this configuration is unable to solve the above problem about brightness unevenness, because it does not suppress the parasitic capacitance C.sub.1 and C.sub.2 between the adjoining pixel electrodes but the parasitic capacitance between the data line and adjoining pixel electrodes.